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What is the assembly instruction endbr32 for?

user618075 edited in Thu, 24 Nov 2022

Endbr32 appears twice in the assembly code in the figure.

1 Replies
commented on Fri, 25 Nov 2022

This is a new instruction added by Intel for control-flow environment technology

The ENDBRANCH (see Section 73 for details) is a new instruction that is used to mark valid jump target addresses of indirect calls and jumps in the program. This instruction opcode is selected to be one that is a NOP on legacy machines such that programs compiled with ENDBRANCH new instruction continue to function on old machines without the CET enforcement. On processors that support CET the ENDBRANCH is still a NOP and is primarily used as a marker instruction by the processor pipeline to detect control flow violations. The CPU implements a state machine that tracks indirect jmp and call instructions. When one of these instructions is seen, the state machine moves from IDLE to WAIT_ FOR_ ENDBRANCH state. In WAIT_ FOR_ ENDBRANCH state the next instruction in the program stream must be an ENDBRANCH. If an ENDBRANCH is not seen the processor causes a control protection exception (#CP), else the state machine moves back to IDLE state.

The target address for the relative jump of technical requirements must be an endbr32 or endbr64 instruction, otherwise it will be abnormal. This instruction does not perform any operation, but is used to verify that the destination address is the expected jump destination.